1. Field of the Invention
The present invention relates to a matched filter bank, particularly to a matched filter bank used in a signal reception apparatus of a DS-CDMA cellular system.
2. Prior Art
Recently, the direct sequence code division multiple access (DS-CDMA) cellular system attracts attention as the users of the land mobile communication increase, because the DS-CDMA system has large capacity. In the DS-CDMA system, at a transmitter side, the transmission data is modulated and then spreaded by a PN-code, and at a receiver side, the received signal is despread by the PN-code so that the transmission data is reproduced. A sliding correlator or a matched filter is used for the despread. The sliding correlator is small in circuit size but needs a long time for the correlation calculation. While, the matched filter is fast in correlation calculation but is rather big in circuit size.
The conventional matched filter consists of a charge coupled device (CCD), a surface acoustic wave (SAW) device, or a digital circuit. A matched filter is proposed in Patent Publication Hei06-164320 by the inventors of the present invention, which consists of an analog circuit and is of high speed as well as low power consumption. The matched filter includes a sampling and holding circuit for holding a plurality of input analog signals as discrete data, a plurality of multiplication circuits for multiplying the analog signals by multipliers that are shifted and circulated and an adder for summing the multiplied data up.
Recently, a plurality of signals, with transmission rates different from one another, are necessary for multi-media communication. Therefore, a spreading ratio is changed (variable spreading ratio system), or two or more spread codes are parallelly used (multi-code system). For these systems, a plurality of matched filters with different number of taps are necessary. It makes the circuits size bigger and the power consumption increases.
The above analog type matched filter proposed by the present inventors uses an inverting amplifier as shown in FIG. 12. The inverting amplifier includes an amplifier AMP with high gain, consisting of odd number of serial CMOS inverters. The amplifier AMP is connected at its input with a plurality of input capacitances CI1 and CI2. A plurality of feedback capacitances Cf1 to Cf6 are connected between the input and output of the amplifier AMP. The feedback capacitances Cf1 to Cf6 are connected to the output of the amplifier AMP through switches MUX1 to MUX6 which connect the feedback capacitanecs to the output of the amplifier or to a reference voltage Vref. For, example, the capacitances Cf1, Cf2, Cf3, Cf4, Cf5 and Cf6 have capacities proportional to 20, 21, 22, 23, 24 and 25, respectively, so various composite capacity can be realized by controlling the switches MUX1 to MUX6. The switches are controlled by control signals S1 to S6 through logical OR-gates G1 to G6 which further receive a refresh signal REF. The signals S1 to S6 are input with inverted to the OR-gate. When the output of the OR-gate is high level, the output of the OR-gates are low level, then the feedback capacitances are connected to the output of the amplifier AMP. When REF is high level or the control signals are low level, the output of the OR-gate is high level, then the feedback capacitances are connected to the reference voltage. The input capacitances CI1 and CI2 are connected at their input to a input refresh switch MUXR1, and an amp-refresh switch SWR is connected between the input and output of the amplifier AMP. The switches MUXR1 and SWR are controlled by the refresh signal REF. When refreshed, the input and output of the amplifier AMP is short-circuited, and CI1 and CI2 are connected to the reference voltage.
When it is assumed that the amplifier AMP has an ideal performance of infinite gain, the input of the amplifier is Vref, input voltages are VI1 and VI2 for CI1 to CI2, the Output of the amplifier is Vo, the weighted addition in the formula (1) is performed.                     Vo        =                                                            -                VI1                            ·              CI1                        -                          VI2              ·              CI2                        +                          Vref              ·                              (                                  CI1                  +                  CI2                  +                  Cf                                )                                              Cf                                    (        1        )            
In a practical amplifier, the input voltage is not Vref and the gain is finite. When the gain is A, the total effective feedback capacitance is CVf, and the total ineffective feedback capacitance is CIf, the output Vo1 is expressed as shown in the formula (2).                     Vo1        =                                                            -                VI1                            ·              CI1                        -                          VI2              ·              cI2                        +                          Vref              ⁡                              (                                  CI1                  +                  CI2                  +                  CVf                                )                                                          CVf            +                                          1                A                            ⁢                              (                                  CI1                  +                  CI2                  +                  CVf                  +                  CIf                                )                                                                        (        2        )            
As will be understood from the formula (2), the error of the output is mainly influenced by a finite gain-bandwidth (GB) product. As the capacity of CIf increases, the error becomes bigger.
The present invention has an object to provide a matched filter bank for a plurality of spreading ratios, not only of low power consumption but also of small circuit size.
The present invention has another object to provide an inverting amplifying circuit, for a matched filter, which is simple, of high accuracy and of quick response.
A matched filter bank according to the present invention has a sampling and holding circuit commonly used by a plurality of matched filters.
An inverting amplifier circuits according to the present invention includes a plurality of feedback capacitances inputs of which are connected to an input of an amplifier or to a reference voltage for controlling a composite valid feedback capcitanec. The invalid capacitances are disconnected from the input of the amplifier.